Artificial intelligence is accelerating how semiconductor companies design and verify chips, but the technology is also creating a new challenge: determining whether AI generated designs can be trusted. As automated systems take on more of the engineering process, companies such as VerifAIX are developing new approaches to verify that those designs remain faithful to their original specifications.
Verification activities can consume up to 70% of an overall chip project’s effort, according to Cadence’s SoC Verification report.
AI could reduce some of that workload, but it also introduces a new challenge. If artificial intelligence can generate parts of a chip faster than engineers can manually review them, the industry needs reliable ways to establish that those designs are actually correct.
That is where a new generation of verification tools is emerging, including VerifAIX, a semiconductor company building what it describes as a verification trust layer for AI driven chip development.
The verification problem is becoming a question of trust
The difficulty is not simply having more code or more components to test. Modern chips combine increasingly complex architectures, protocols, interfaces and software defined functionality. Engineers need to establish that those pieces behave according to the original design requirements, including edge cases that may not be obvious from the implementation itself.
The numbers show why the problem remains difficult. Only 14% of IC/ASIC projects achieved first silicon success in the 2024 Wilson Research Group study, the lowest rate recorded in two decades. The findings are detailed in the 2024 Wilson Research Group IC/ASIC Functional Verification Trend Report.
AI can help reduce the amount of manual work involved in verification, but generating more verification artifacts does not necessarily establish that the underlying design is correct.
That distinction becomes particularly important as AI begins generating parts of the design itself.
Cadence, for example, launched its ChipStack AI Super Agent in February 2026 to automate parts of chip design and verification. The company reported productivity improvements of up to 10X across tasks including RTL and testbench development, verification planning, regression management and debugging.
At the same time, the semiconductor industry is exploring ways to establish a more reliable reference point for verification. Semiconductor Engineering reported in June that companies are working toward a “golden” specification above RTL that can connect requirements to implementation and verification while identifying gaps, conflicts and inconsistencies.
VerifAIX is building a verification layer around design intent
This is the problem VerifAIX is targeting.
The semiconductor verification company has raised $5 million in seed funding co led by Endiya Partners and Bluehill VC. The round is its first major institutional funding and will support product development, customer deployments and engineering expansion across the US, India and Israel.
Its approach is built around what the company calls a “Formal Brain,” which combines AI reasoning with mathematically grounded methods to understand specifications and intended behavior.
Rather than treating verification as a collection of independent checks, the platform is designed to reason across specifications, design implementations and verification assets. It can then identify inconsistencies or gaps and use that understanding to drive formal verification, simulation, coverage, debugging and verification closure.
The idea is particularly relevant to AI generated designs because the system creating an implementation is not necessarily the best source for determining whether that implementation is correct.
“AI is changing how semiconductor designs are created, but generating a design is not the same as proving that it is correct,” said Madhulima Tewari, CEO of VerifAIX. “The industry urgently needs an independent layer of trust that can establish correctness and preserve traceability to design intent, and we’re building that. This funding enables us to deepen the technology, expand our engineering capabilities and take the platform to increasingly complex designs and a growing set of customers.”
VerifAIX has already been deployed at semiconductor companies on real world verification challenges, including designs involving complex control logic and protocols. The company was founded by Tewari, Kenneth Roe and Avner Landver, whose backgrounds span AI, EDA, formal verification and semiconductor engineering.
The company is entering a market where established EDA vendors are also moving toward more autonomous workflows.
In June, Cadence introduced a fully autonomous version of its ChipStack platform that uses AI agents to run dynamic simulations and formal verification. The company reported more than 40X faster RTL validation cycles in deployments, reducing a typical five week verification loop to less than a day.
That kind of acceleration could change the economics of chip development, but it also highlights the importance of knowing what those automated systems have actually established.
For VerifAIX, the answer is to put mathematical rigor underneath the AI rather than relying on the model itself as the final authority.
As AI takes on more of the work involved in designing chips, verification is likely to become less about simply checking more outputs and more about establishing a reliable chain between what engineers intended, what AI generated and what can ultimately be proven correct.
That could make verification not the brake on AI driven chip development, but the layer that determines how far that acceleration can safely go.
Disclosure: This article mentions a client of an Espacio portfolio company.
